`default_nettype none

module SerializerTestbed (clkin, dout, hi_in, hi_out, hi_inout, hi_muxsel, i2c_sda, i2c_scl);

input wire			clkin; // 166MHz input clock
output wire			dout; // serial data out

// Opal-Kelly Host Interface - USB chip connection
input	wire [7:0]	hi_in;
output	wire [1:0]	hi_out;
inout	wire [15:0]	hi_inout;
output	wire		hi_muxsel;
output	wire		i2c_sda;
output	wire		i2c_scl;

assign hi_muxsel = 1'b0;
assign i2c_sda = 1'bz;
assign i2c_scl = 1'bz;

// Opal Kelly Host Interface internal connections
wire [30:0]		ok1;

// DCM clocks
wire	clk1x; // 12ns (83.3MHz) DCM clock
wire	clk2x; // 6ns (166MHz) DCM clock
wire	clk4x; // 3ns (333MHz) DCM clock

wire	clk1xdcm;
wire	clk2xdcm;
wire	clk4xdcm;

// parallel data
wire [7:0]	din;

// Opal Kelly Host
okHost okHI	(	.hi_in( hi_in ),
				.hi_out( hi_out ),
				.hi_inout( hi_inout ),
				.ti_clk( ),
				.ok1( ok1 ),
				.ok2( )
			);
   
// Opal Kelly wires from PC
okWireIn ep00 (	.ok1(ok1), // control wires
				.ep_addr(8'h00),
				.ep_dataout( din )
				);

DCM_SP #(
	.CLK_FEEDBACK 	("1X"),
	.CLKDV_DIVIDE	(2.0),
	.CLKIN_PERIOD	("6.0"),
	.DESKEW_ADJUST	("0"),	
	.CLKFX_MULTIPLY	(2),
	.CLKFX_DIVIDE	(1))	
dcm_clk (
	.CLKIN   	(clkin),
	.CLKFB   	(clk2x),
	.DSSEN 		(1'b0),
	.PSINCDEC	(1'b0),
	.PSEN 		(1'b0),
	.PSCLK 		(1'b0),
	.RST     	(1'b0),
	.CLK0    	(clk2xdcm),
	.CLK90   	(),
	.CLK180  	(),
	.CLK270  	(),
	.CLK2X   	(clk4xdcm),
	.CLK2X180	(),
	.CLKDV   	(clk1xdcm),
	.CLKFX   	(),
	.CLKFX180	(),
	.LOCKED  	(),
	.PSDONE  	(),
	.STATUS  	());

BUFG bufg_1x	( .I(clk1xdcm),		.O(clk1x) ) ;
BUFG bufg_2x	( .I(clk2xdcm),		.O(clk2x) ) ;
BUFG bufg_4x	( .I(clk4xdcm),		.O(clk4x) ) ;

Serializer8 serializer (
	.clk1x(clk1x),
	.clk2x(clk2x),
	.clk4x(clk4x),
	.din(din),
	.dout(dout));

endmodule

